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TECHNICAL NOTE
Sound Path Selector LSI Series
Mixer & Selector With 16bit D/A Converters
BU7858KNBU7893GU
OUTLINE This LSI is mounted with stereo 16bit D/A Converter and suitable for higher sound quality and miniaturization of cellular phone with music play. BU7893GU has a 3D surround enhancement function and hence can play the wide-spreading stereo sound from stereo speakers that are arranged nearby.
FEATURE 1) Mounted with Stereo 16bit audio D/A converter 2) Compatible with Stereo analogue interface 3) Stereo headphone amplifier (16) 4) Low-band corrective circuit in headphone amplifier 5) Volume that can adjust the gain 6) Flexible mixing function
APPLICATION Portable information & communication equipments such as cellular phone and PDA (Personal Digital Assistant) etc. Cellular phone with music play
LINEUP Function Stereo audio D/A converter Stereo audio interface format BU7858KN 16bit 16bit Right justified 18bit Right justified IIS No No 16 driver Yes Built-in Yes (headphone only) VQFN28 BU7893GU 16bit 16bit Left justified 16bit Right justified IIS Yes Yes 16 driver No Built-in Yes VCSP85H3
3D surround enhancement function 3 band equalizer Stereo headphone amplifier Line output (600 driver) Headphone amplifier low-band correction function Click noise reduction function Package
Oct. 2007
ABSOLUTE MAXIMUM RATINGS Parameter Power-Supply BU7858KN Voltage BU7893GU Power Dissipation
Symbol VDD DVDDIO AVDD DVDDCO
Rating -0.3 4.5 -0.3 4.5 -0.3 2.5
Unit V V
BU7858KN 580 *1 Pd mW BU7893GU 700 *2 -20 +85 Operating BU7858KN TOPR -30 +85 Temperature BU7893GU -55 +125 Storage BU7858KN TSTG -50 +125 Temperature BU7893GU *1 5.8mW is decreased every 1 when using it over 25. (mounted on the ROHM standard PCB ) *2 7.0mW is decreased every 1 when using it over 25. RECOMMENDED OPERATING CONDITION BU7858KN Parameter Symbol Power-Supply Voltage VDD BU7893GU Parameter Analog Power-Supply Voltage Digital I/O Power-Supply Voltage Digital Core Power-Supply Voltage ELECTRICAL CHARACTERISTICS BU7858KN Unless otherwise specifiedTa=25AVDD=DVDD=3.0V Analog Parameter Symbol Min Typ Current Consumption Idd3 2.3 DAC S/(N+D) DAC S/N Headphone Amplifier Total Harmonic Distortion Headphone Amplifier Maximum Output Headphone Amplifier Output Noise Voltage SPO Maximum Output Level EXTO Maximum Output Level Digital (DC) Parameter Digital Input Voltage "L" Digital Input Voltage "H" Digital Output Voltage "L" Digital Output Voltage "H" Input Leakage Current 1 Symbol VIL VIH VOL VOH IIN1 Min 0.8 x DVDD DVDD -0.5 Typ Max 0.2 x DVDD 0.5 2 Unit V V V V A Iol=-500A Ioh=500A at 0V, 3V Condition SN+D SNR THDhp PO VNO VOMAX1 VOMAX2 2.0 2.0 85 92 0.05 10 -94 Symbol AVDD DVDDIO DVDDCO Min 2.6 DVDDCO 1.62 Typ 2.8 1.8 1.8 Max 3.3 3.3 1.98 Unit V V V
Min 2.7
Typ 3.0
Max 3.3
Unit V
Max 3.7 0.5 -80
Unit mA dB dB % mW dBV VP-P VP-P
Condition 16 driver part and no signal fs=44.1kHz, fin=1kHz, 20kHz LPF, Vin=-0.5dBFS fs=44.1kHz, fin=1kHz , A-weighted, Vin=0dBFS fin=1kHz, 20kHz LPF, Vin=-10dBV fin=1kHz, THD=10%, RL=16 A-weighted fin=1kHz, THD1%, 10kLoad fin=1kHz, THD1%, 600Load
2/24
Audio Interface Parameter MCLKI Frequency MCLKI Duty Ratio LRCLK Frequency LRCLK Duty Ratio BCLK Frequency BCLK Duty Ratio LRCLK edge to BCLK Time BCLK to LRCLK Edge Time Data Hold Time Data Set-up Time Symbol fMCLK dMCLK fs dLR fBCK dBCK tLRS tSLR tSDH tSDS Min 4.096 45 16 45 0.512 45 50 50 50 50 Typ Max 18.432 55 48 55 3.072 55 Unit MHz % kHz % MHz % ns ns ns ns Condition
BU7893GU Whole Block Unless otherwise specifiedTa=25DVDD_CORE=1.8VDVDD_IO=1.8VAVDD=2.8VDigital input terminal is fixed with DVDD_IO "L" or "H" levelThe gain settings of the audio paths are all 0dB, and no signal Parameter Symbol Min Typ Max Unit Condition DVDD_CORE Stand-by Current ISTCO 10 A standbyCLKI = DVSS (Core logic block) DVDD_IO Stand-by Current ISTIO 5 A standbyCLKI = DVSS AVDD Stand-by Current ISTA 5 A standby DVDD_CORE Operation Current IDDCO 5 10 mA BCLKLRCLK = Input mode DVDD_IO Operation Current IDDIO 0.1 1 mA MCLK = L output ANAINLMIX1SPOL AVDD Operation Current 1 IDDA1 1.6 2.8 mA (Analog melody) ANAINRMIX2SPOR SDIMIX1SPOL AVDD Operation Current 2 IDDA2 6.0 10.0 mA SDIMIX2SPOR (Digital melody) TCXOI = 19.8MHzfs = 44.1kHz DC Characteristic Parameter L Output Voltage H Output Voltage L Level Input Voltage1 L Level Input Voltage 2 H Level Input Voltage 1 H Level Input Voltage 2 L Level Input Current H Level Input Current 1 H Level Input Current 2 Output OFF Current
Termin -al Vold Vohd Vild1 Vild2 Vihd1 Vihd2 Iild Iihd1 Iihd2 Iozd
Symbol All output terminal1 All output terminal1 All input 2 terminal CLKI
3
Min 0 DVDD_IO -0.30 -0.3 -0.3 DVDD_IO -0.5 3 -1 -1 -1 -10
Typ
Max 0.30 DVDD_IO DVSS+0.5 3 DVDD_IO +0.3 DVDD_CORE +0.3 1 1 1 10
Unit V V V V V V A A A A
Condition Iol=+0.8mA Ioh=-0.8mA
All input 2 terminal CLKI3 All input terminal2 All input 2 terminal CLKI3 Hi-Z terminal4
Input terminal voltage is DVSS Input terminal voltage is DVDD_IO Input terminal voltage is DVDD_CORE
1 : They also contain interactive terminals that are set output state. 2 : They also contain interactive terminals that are set input state. 3 : Please connect 100pF coupling capacitor and input 0.5VP-P or more when you input through coupling capacitor. (In address 15h CLKSEL1=0CLKSEL0=1) 4 : At interactive terminals of input state or three-state terminals of output-disable state
3/24
Audio Path(MIX) Unless otherwise specifiedTa=25AVDD=2.8Vreference input level=-6dBVf=1kHzA-weighted path gain =0dB Condition Parameter Symbol Min Typ Max Unit 1dB step ANAL_V Volume Setting GDACL -11 +3 dB 1dB step ANAR_V Volume Setting GDACR -11 +3 dB Audio Path (SP PREamp) Unless otherwise specifiedTa=25AVDD=2.8Vreference input level =-6dBVf=1kHzA-weightedpath gain =0dB RL=33k Condition Parameter Symbol Min Typ Max Unit 20kHz LPF THD+N THDSP -70 -60 dB Output Noise Voltage VNOSP -90 -80 dBV At no a signal Mute Level MLSP -90 -80 dB 1kHz BPF Audio Path (HP amp) Unless otherwise specifiedTa=25AVDD=2.8Vreference input level =-6dBVf=1kHzA-weightedpath gain =0dB RL=16 Condition Parameter Symbol Min Typ Max Unit 20kHz LPF THD+N THDHP -65 -55 dB Output Noise Voltage VNOHP -90 -80 dBV At no signal The Maximum Output Power POHP 10 mW THD=10%16 load Channel Separation CSHP -80 -70 dB Vo=-14dBV1kHz BPF Mute Level MLHP -90 -80 dB 1kHz BPF HPL_V Volume Setting 1 GA1HPL -48 0 dB 2dB step HPL_V Volume Setting 2 GA2HPL -42 +6 dB 2dB step HPR_V Volume Setting 1 GA1HPR -48 0 dB 2dB step HPR_V Volume Setting 2 GA2HPR -42 +6 dB 2dB step
3D Surround, Equalizer, and Audio DAC Unless otherwise specifiedTa=25AVDD=2.8VBCLK=64fsLRCLK=256fsf=1kHz path gain=0dBSPOL/SPOR outputSPOL/SPOR= no loadoutput=0dBFS Condition Parameter Symbol Min Typ Max Unit Full-scale Amplitude VMAX 1.40 1.68 2.00 VP-P 0.6xAVDD S/N1 (A-Weighted) DACsn1 70 75 dB THD+N1 (20kHz LPF) DACthd1 -70 -60 dB fs=811.025kHz THD+N2 (20kHz LPF) DACthd2 -75 -65 dB fs=1622.053244.148kHz
Audio I/F Format Unless otherwise specifiedTa=25DVDD_IO=1.623.3VDVDD_CORE=1.621.98V Parameter Symbol Min Typ Max Unit 64fs BCLK Output Frequency FBCKO 0.512 3.072 MHz LRCLK Output Frequency FLRCKO 8 48 kHz SDI Set-up Time tSDSU 100 nsec SDI Hold Time tSDH 100 nsec
Condition
PLL Unless otherwise specifiedTa=25AVDD=2.8VBCLK = no load Parameter Symbol Min Typ Max PLL Lock-up Time Tlock1 10 PLL Jitter Tjitter1 200
Unit msec psec
Condition BCLK terminalfVCO=65.536MHz
4/24
REFERENCE DATA BU7858KN
10.0 STAND-BY CURRENT : ICC (A) OPERATION CURRENT : ICC (mA) 8.0 6.0 4.0 2.0 0.0 2.0 2.5 3.0 3.5 4.0 4.5 SUPLLY VOLTAGE : VDD(V)
12.0 10.0 8.0 6.0 4.0 2.0 0.0 2.0 2.5 3.0 3.5 4.0 4.5 SUPLLY VOLTAGE : VDD(V)
OPERATION CURRENT : ICC (mA)
14.0
6.0 5.0 4.0 3.0 2.0 1.0 0.0 2.0 2.5 3.0 3.5 4.0 4.5 SUPLLY VOLTAGE : VDD(V)
Fig.1 Stand-by Current
Fig.2 16bit D/A Converter Operation Current
-30 -40 -50
THD+N (dB)
Fig.3 Headphone Amplifier Operation Current
-30 -40 -50 THD+N (dB) -60 -70 -80 -90 -100 -110
-30 -40 -50
THD+N (dB)
-60 -70 -80 -90 -100 -110 -120 -110 -90 -70 -50 -30 -10 INPUT LEVEL : VIN(dBFS)
-60 -70 -80 -90 -100 -110 -120 -110 -90 -70 -50 -30 -10 INPUT LEVEL : VIN(dBFS)
-120 10 100 1000 10000 100000 INPUT SIGNAL FREQ : FIN(Hz)
Fig.4 16bit D/A Converter Total Harmonic Distortion (Lch)
Fig.5 16bit D/A Converter Total Harmonic Distortion (Rch)
Fig.6 16bit D/A Converter Total Harmonic Distortion (Lch)
-30 -40 -50 THD+N (dB) -60
THD+N (%)
100.00
100.00
10.00 THD+N (%)
10.00
-70 -80 -90 -100 -110 -120 10 100 1000 10000 100000 INPUT SIGNAL FREQ : FIN(Hz)
1.00
1.00
0.10
0.10
0.01 -100 -80 -60 -40 -20 0 INPUT LEVEL : VIN(dBV)
0.01 -100
-80
-60
-40
-20
0
INPUT LEVEL : VIN(dBV)
Fig.7 16bit D/A Converter Total Harmonic Distortion (Rch)
100.00
Fig.8 Headphone Amplifier Total Harmonic Distortion (HP_L)
100.00
Fig.9 Headphone Amplifier Total Harmonic Distortion (HP_R)
10.00 THD+N (%) THD+N (%) -80 -60 -40 -20 0
10.00
1.00
1.00
0.10
0.10
0.01 -100 INPUT LEVEL : VIN(dBV)
0.01 -100 -80 -60 -40 -20 0
INPUT LEVEL : VIN(dBV)
Fig.10 SPO Total Harmonic Distortion
Fig.11 EXTO Total Harmonic Distortion
5/24
BU7893GU
OPERATION CURRENT : ICC (A)
2.6 2.8 3.0 3.2 3.4
5.0
STAND-BY CURRENT : ICC (A) STAND-BY CURRENT: ICC (A)
5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0
5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 1.6 1.7 1.8 1.9 2.0 SUPLLY VOLTAGE : DVDD_CORE(V)
4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 1.6 1.7 1.8 1.9 2.0 SUPLLY VOLTAGE : DVDD_CORE(V)
SUPLLY VOLTAGE : AVDD(V)
Fig.12 DVDD_CORE Standby Current
2.0 1.9 1.8 1.7 1.6 1.5 1.4 2.6 2.8 3.0 3.2 3.4 SUPLLY VOLTAGE : AVDD(V)
Fig.13 AVDD Standby Current
5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.6 1.7 1.8 1.9 2.0 SUPLLY VOLTAGE : DVDD_CORE(V) 4.0 3.9 3.8 3.7 3.6 3.5 3.4 3.3 3.2 3.1 3.0
Fig.14 DVDD_CORE Operation Current (Analog melody)
OPERATION CURRENT : ICC (mA)
OPERATION CURRENT : ICC (mA)
OPERATION CURRENT : ICC (mA)
2.6
2.8
3.0
3.2
3.4
SUPLLY VOLTAGE : AVDD(V)
Fig.15 AVDD Operation Current (Analog melody)
Fig.16 DVDD_CORE
Operation Current (digital
melody)
0.0 -10.0 -20.0 THD+N (dB) THD+N (dB) -30.0 -40.0 -50.0 -60.0 -70.0 -80.0 -90.0 0.0 -10.0 -20.0 -30.0 -40.0 -50.0 -60.0 -70.0 -80.0 -90.0 -80 -60 -40 -20 0
Fig.17 AVDD Operation Current (digital melody)
0.0 -10.0 -20.0
THD+N (dB)
-30.0 -40.0 -50.0 -60.0 -70.0 -80.0 -90.0 -100 -80 -60 -40 -20 0 INPUT LEVEL (dBFS)
-100
10
100
1000
10000
100000
INPUT LEVEL (dBFS)
INPUT SIGNAL FREQUENCY (Hz)
Fig.18 16bit D/A Converter Total Harmonic Distortion 1kHz (SPOL)
0.0 -10.0 -20.0 THD+N (dB)
Fig.19 16bit D/A Converter Total Harmonic Distortion 1kHz (SPOR)
100.00
Fig.20 16bit D/A Converter Total Harmonic Distortion (SPOL)
100.0
10.00
THD+N (%) THD+N (%)
10.0
-30.0 -40.0 -50.0 -60.0 -70.0 -80.0 -90.0 10 100 1000 10000 100000 INPUT SIGNAL FREQUENCY (Hz)
1.00
1.0
0.10
0.1
0.01 -100 -80 -60 -40 -20 0 INPUT LEVEL (dBV)
0.0 -100 -80 -60 -40 -20 0 INPUT LEVEL (dBV)
Fig.21 16bit D/A Converter Total Harmonic Distortion (SPOR)
Fig.22 Headphone Amplifier Total Harmonic Distortion (HPOL / HPOR) 6/24
Fig.23 Speaker Preamp Total Harmonic Distortion (SPOL / SPOR)
BLOCK CHART BU7858KN
PLLC
DV DD
DVSS
AVDD
AVSS
MCLKO
PLL
MIXSEL1 SW1
BCLK
ATT2
+ SPO
SP Amp
RXI RING
+
SW2
ATT1
MIXSEL2
ATT3
+ EXTO 600 16 HP_R
MCLKI BCLK LRCLK SDTI
Digital Audio I/F
Digit -al ATT
16bit DAC
LPF
ATT
MIXSEL3
+ -
ATT4
+ 16
CA_R HP_L
16bit DAC
LPF
MIXSEL4
MEL_R MEL_L EXTI
ATT5
CA_L
ATT
BIAS
Serial Control
CVCOM
NRST
SCLK SDATA
SCS
CSTEP
CSTART
Fig.24 BU7858KN Block Diagram
AVSS
AVDD
21
20
19
EXTO
18
17
16
HP_L
SPO
MEL_L 22
CA_L 15
EXTI
14 CA_R
MEL_R 23
13 HP_R
RING 24
12 CVCOM
RXI 25
BU7858KN
11 CSTART
PLLC 26
10 CSTEP
MCLKO 27 MCLKI 28
9 NRST 8 NCS
1 SDTI
2 LRCLK
3 BCLK
4 DVDD
5 DVSS
6 SCLK
7 SDATA
Fig.25
BU7858KN Pin Assignment (TOP VIEW)
7/24
BU7893GU
Serial I/F
1F
1F
1F
0.1F
CSTEP
CPOP
RSTB SCLK SO SIO
CSB
COMOUT COMIN DVSS DVDD_IO DVDD_CORE AVSS AVDD
CPOP
SPI
VREF
CCL
Stereo Analog Interface (From Melody LSI)
ANAINL ANAINR CLKI PLLC
PLL
VOL VOL
-6dB +
RX EXT DACL DACR RX -6dB EXT DACL DACR
VOL
+
HPOL
6800p 100 16
19.2MHz/ 19.68MHz/ 19.8MHz
VOL
+
HPOR CCR
6800p
100 16
RX EXT DACL
MCLK
Stereo PCM Interface (MP3,AAC,etc)
SPOL
SP Amp 8
DAI
Equalizer
-6dB
DAC
Fig.26
BU7893GU Block Diagram
1 A B C D E F
2
3
TEST3 CCR SCLK SIO CSB TEST2
HPOR RSTB SO MCLK PLLC CLKI
HPOL DVSS
AVDD DVDD_IO
( TOP VIEW ) Fig.27 BU7893GU Ball Assignment
+
LRCLK BCLK SDI
DAC
-6dB
DACR RX EXT DACL DACR
Sonaptic 3D
SPOR
SP Amp 8
4
5
6
CPOP CCL
SPOL SPOR CSTEP COMOUT
TEST4 COMIN AVSS ANAINR ANAINL TEST1
DVDD_CORE
SDI LRCLK
BCLK
8/24
DIGITAL INTERFACE OF 16BIT AUDIO D/A CONVERTER 16bit audio D/A converter equipped with this series can be used with the following audio format. BU7858KN 1) MSB first 16bit data (Right justified)
LRCLK(fs)
Lch Rch
BCLK(64fs
SDTI
2
1
0
Don't
Care
15
14
13
12
11
4
3
2
1
0
Don't
Care
15
14 13
12 11
4
3
2
1
0
15:MSB, 0:LSB
2) MSB first 18bit data (Right justified)
LRCLK(fs)
Lch Rch
BCLK(64fs
SDTI
2
1
0
Don't
Care
17
16
15
14
11
4
3
2
1
0
Don't
Care
17
16 15
14 11
4
3
2
1
0
17:MSB, 0:LSB
3) IIS mode 18bit data (Left justified)
LRCK(fs)
Lch Rch
BCLK(64fs)
SDTI
Don't
17
16
4
3
2
1
0
Don't
Care
17
16
4
3
2
1
0
Don't
Care
17
16
17:MSB, 0:LSB
4) IIS mode 16bit data (BCLK=32fs)
LRCLK(fs)
Lch Rch
BCLK(32fs) SDTI
2 1 0 15 14 13 12 11 10 9 8 7 6 3 2 1 0 15 14 13 12 11 10 9 8 7 6 3 2 1 0 15 14 13
15:MSB, 0:LSB
Fig.28
AUDIO I/F FORMAT (BU7858KN)
BU7858KN is provided with a mode that generates MCLK (Master Clock) by using the built-in PLL, so it is possible to make a D/A converter operate even if the clocks are only BCLK (64fs/32fs), LRCLK (fs). The PLL generates MCLK (Master Clock), which is necessary for driving of D/A converter, from BCLK (Bit Clock). Please connect a capacitor (PLLC) for the filter with DVSS. Moreover, please place the capacitor nearest DVSS of IC in order to reduce the noise interference. Then it is possible to monitor the master clock that is generated internally from MCLKO, which is after all the monitor terminal, and hence does not guarantee drivability and phase-margin. Please tie the MCLKI terminal to DVSS when PLL is used. And please tie the PLLC terminal to DVSS when PLL is not used. Moreover, it is not necessary to set the "PLLPDN" and "SMPR" when PLL is not used.
9/24
BU7893GU
1.MSB first left justified format MSB
LRCLK 0 BCLK SDI 15 14 13 2 1 0
Don't care Don't care
Lch 1 2 3 13 14 15 16 17 18 29 30 31 0 1 2 3
Rch 13 14 15 16 17 18 29 30 31 0
15 14 13
2
1
0
Don't care
Don't care
15
2. MSB first right justified format MSB
SDI
Don't care
15 14 13
2
1
0
Don't care
Don't care
15 14 13
2
1
0
Don't care
3. IIS IIS format
LRCLK 0 BCLK 1 2 3 4 Lch 14 15 16 17 18 19 30 31 0 1 2 3 4 Rch 14 15 16 17 18 19 30 31 0
SDI
Don't care
15 14 13
2
1
0
Don't care
Don't care
15 14 13
2
1
0
Don't care
Don't care
Fig.29
AUDIO I/F Format (BU7893GU)
3D SURROUND ENHANCEMENT FUNCTION BU7893GU Even under the circumstances of adjacent arrangement of stereo speakers, the wide-spreading acoustic effect can be achieved because of the output resulting from the digital audio input to which the 3D surround effect has been applied. Moreover, the stereo sound at the time of audio recording can also be played truly. Please tell us about the parameter setting when you use this function.
LOW-BAND CORRECTIVE CIRCUIT In the headphone output terminals (HP_L, HP_R or HPOL, HPOR), there is a low-band corrective circuit, which corrects the low-band attenuation.
200k 200k 100k + CL + HP_X or HPOX RL CCHPx CA_X or CCX OUTPUT
Fig.30 BU7858KN & BU7893GU Headphone Output Equivalent Circuit Low-band cut-off frequency Low-band boost frequency Boost gain fC= 1/(2CLRL) fBOOST = 1/(2CCHPx200k) ABOOST = 20log((200 k+1/(2fCCHPx))/100 k) the maximum low-band boost is 6dB
For parameter setting, determine the output coupling capacitance CL and the headphone impedance RL before calculating the low-band cut-off frequency fC. Then determine CCHPx so that the low-band cut-off frequency fC is roughly in agreement with the low-band boost frequency fBOOST. The recommended parameter setting of BU7858KN and BU7893GU is CCHPx = 6800pF at the time of CL = 100F and RL = 16.
10/24
The frequency characteristic (theorical value) when the recommended constants are used is shown below.
10 5 0 -5 -10 Gain [dB] -15 -20 -25 -30 -35 -40 1 10 100 Frequency [Hz] 1000 10000 100000
Amplifier output
After correction Before correction
Fig.31
Low-band corrective circuit Frequency characteristic
CPU INTERFACE BU7858KN and BU7893GU can be controlled by using CPU interface. BU7858KN NCS
tcs tcyc tch
SCLK
tds tdh
A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
SDATA
A7
Fig.32
CPU I/F Timing Chart 1 (BU7858KN)
After the falling edge of NCS, SDATA inputs are settled by 16 clock of SCLK, and data is written in the rising edge of NCS. The data format is "16bit right justified". CPU interface is that 1Byte=16bit. It is absolutely necessary to insert the interval of NCS="H" between first Byte and Second Byte because it is not compatible with continuous data transmission. For the following th, please wait the time more than 1 SCLK Clock. (thtcyc)
th NCS
SCLK
S D A TA
Fig.33
CPU I/F Timing Chart 2 (BU7858KN)
AC Characteristics Ta=25AVDD=DVDD=3.0V Item Symbol Min Typ SCLK Width tcyc 250 SDATA Input Hold Time tdh 50 SDATA Input Set-up Time tds 50 NCS Set-up Time tcs 50 NCS Hold Time tch 50 It is recommended to use exclusive lines for CPU interface.
Max -
Unit ns ns ns ns ns
Conditions
11/24
BU7893GU Timing Chart
SCLK
Tsc
SIO AD[6] AD[5]
Thc
AD[4] AD[0] Direction DT[7] DT[6] DT[1] DT[0]
SEL When direction is "1": When direction is "0": Write operation Read operation
Tscss
Write Operation
SCLK
SIO
AD[6]
AD[5]
AD[4]
AD[0]
Direction"H"
DT[7]
DT[6]
DT[1]
DT[0]
SEL
Read Operation (mode 1):
SCLK
SO_ENABLE (bit0 at register address 14h)=0
Tsd
SIO AD[6] AD[5] AD[4] AD[0] Direction"L" SEL Output data Hi-Z DT[7] DT[6] DT[1]
DT[0]
Read Operation (mode 2):
SCLK
SO_ENABLE (bit0 at register address 14h)=1
Tsd
SIO AD[6] AD[5] AD[4] AD[0] Direction"L" SO DT[7] DT[6] DT[5] DT[1] DT[0]
Hi-Z
Hi-Z
SEL
Output data
Fig.34 CPU I/F Timing Chart (BU7893GU) DVDD_IO=1.623.3VTa=-30+85 Item Symbol Min Typ Max Unit Conditions Bit Length Ncha 16 bit MSB first SCLK Input Frequency FSCLK 15 MHz SCLK `L' Pulse Width Tlsclk 25 ns SCLK `H' Pulse Width Thsclk 25 ns SCLK-SEL Set-up Time Tscss 10 ns Data Set-up Time Tsc 10 ns Data Hold Time Thc 10 ns SIO: Time from SCLK falling edge Delay Time of Data Output Tsd 30 ns SO : Time from SCLK rising edge It is recommended to use exclusive lines for CPU interface. 12/24
I C INTERFACE BU7893GU 2 In the BU7893GU, the LSI can be controlled by using I C interface.
2 The device's address (slave address) is "1100011(63h)". It is based on the Philips I C-BUS V2.1's fast-mode, the
2
maximum transfer rate of a bit is 400kbps. A7 1 A6 1 A5 0 A4 0 A3 0 A2 1 A1 1 W/R 0/1
I2C Slave addresses
Bit Transfer A data is transferred during the HIGH period of the clock . The data on the SIO line must be stable during this period. The HIGH or LOW state of the data line can only change when the clock signal on the SCLK line is LOW. When SCL is H and SDA changes, the START conditions or the STOP condition is generated, and it is interpreted as the control signal.
SIO SCLK SIO is stable. Valid Data SIO is possible to change
START & STOP Conditions When SIO and SCLK are "H", there is no data transfer performed on the I2C bus. A HIGH to LOW transition on the SIO line while SCLK is HIGH is one such unique case. This situation indicates a START condition (S). A LOW to HIGH transition on the SIO line while SCLK is HIGH defines a STOP condition (P).
SIO SCL
S START conditions
P STOP conditions
The consecutive START and STOP conditions are acceptable.
Acknowledge After START condition, 8 bits of data is transferred at a time. The transmitter releases the SIO line, and the receiver returns the Acknowledge signal by assuming SIO to be "L".
SIO output by the transmitter SIO output by the receiver Non-Acknowledge Acknowledge SCLK S 1 2 8 Clock pulse for Acknowledge 9
START condition
13/24
Writing Protocol The write protocol is shown below. The register address is transferred in a byte after the slave address and write command are transferred. The third byte writes the data into the internal register that is indicated by the second byte. After that, the register address is incremented on automatically (when the register address is between 00h and 16h). However, when the register address reaches 16h, the register address does not change with the next byte transfer, rather, it accesses the same register address (16h). The register address is incremented after transfer completion.
S 1 1 0 0 0 1 1 0 A A7 A6 A5 A4 A3 A2 A1 A0 A D7 D6 D5 D4 D3 D2 D1 D0 A Register address R/W=0(Write) Data Register address Increment D7 D6 D5 D4 D3 D2 D1 D0 A Data Register address Increment P
Slave address
from master to slave
from slave to master
A=Acknowledge A=Non-Acknowledge S=START condition P=STOP condition
Reading Protocol It reads from the next byte after writing the slave address and R/W bit. The read register is the following address accessed at the end. After that, the data of the address incremented is read out. after transfer completion.
S 1 1 0 0 0 1 1 1 A D7 D6 D5 D4 D3 D2 D1 D0 A Data R/W=1(Read) Register address Increment A=Acknowledge A=Non-Acnkowledge S=START condition P=STOP condition D7 D6 D5 D4 D3 D2 D1 D0 A Data Register address Increment P
The register addresses are incremented
Slave address
from master to slave from slave to master
Combined Reading Protocol After specifying an internal address, it reads by generating resending start conditions and changing the direction of data transfer. Afterwards, data from incremented addresses is read. The register addresses are incremented after transfer
completion. Compound writing is possible by writing R/W=0 after resending start condition.
S 1 1 0 0 0 1 1 0 A A7 A6 A5 A4 A3 A2 A1 A0 A Sr 1 Register address R/W=0 ( Write) 1 0 0 0 1 1 1 A
Slave address
Slave address R/W=1 ( Read)
D7 D6 D5 D4 D3 D2 D1 D0 A Data Register address Increment
D7 D6 D5 D4 D3 D2 D1 D0 A Data
P
from master to slave
from slave to master
A=Acknowledge A=Non-acknowledge S=START condition P=STOP condition Sr=Repeated START condition
Register address Increment
14/24
Timing Diagram
Repeated START conditions
BIT 7
BIT 6
Acknowledge
STOP condition
t SU;STA SCL SIO
tLOW t HIGH 1/fSCLK
t BUF t HD;STA
tSU;DAT t HD;DAT
2 Fig.35 I C Timing Diagram
tSU;STO
DVDD_IO=1.623.3VTa=-30+85 Item Hold Time at Start Condition SCLK "H" Level Time SCLK "L" Level Time Set-up Time for Repeated Start Condition Data Hold Time Data Set-up Time Set-up Time for Stop Condition Bus Release Time between Stop Condition and Start Condition
Symbol tHD;STA tHIGH tLOW tSU;STA tHD;DAT tSU;DAT tSU;STO tBUF
Min 0.6 0.6 1.3 0.6 0 100 0.6 1.3
Typ
Max 0.9
Unit sec sec sec sec sec nsec sec sec
Conditions
PIN FUNCTION Equivalent Circuit Diagram A A A A A A A C G
BU7858KN No. 1 2 3 4 5 6 7 8 9 10 11 Pin Name SDTI LRCLK BCLK DVDD DVSS SCLK SDATA NCS NRST CSTEP CSTART I/O Pin Function Power DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD AVDD AVDD
I Audio DAC Serial Data Input I Audio DAC LR Clock I Audio DAC BIT Clock - Digital Power Supply - Digital Ground I Serial Clock for CPU Interface I Serial Data for CPU Interface I Serial Chip Selection for CPU Interface I Reset Input L: Reset
- Capacitor Connection Terminal for Pop Noise Reduction Capacitor Connection Terminal for Pop Noise Reduction at Start-up Capacitor Connection Terminal for Internal Reference Voltage Output
12 13 14
CVCOM HP_R CA_R
-
AVDD AVDD AVDD
G H C
O Headphone Amplifier Output R-ch Low-band Correction Capacitor for Headphone Amplifier R-ch
15/24
No.
Pin Name
I/O
Pin function Low-band Correction Capacitor for Headphone Amplifier L-ch
Power
Equivalent Circuit Diagram C H H H D D D E D C B A
15 16 17 18 19 20 21 22 23 24 25 26 27 28
CA_L HP_L AVSS AVDD EXTO SPO EXTI MEL_L MEL_R RING RXI PLLC MCLKO MCLKI
-
AVDD AVDD AVDD AVDD AVDD AVDD AVDD AVDD AVDD DVDD DVDD DVDD
O Headphone Amplifier Output L-ch - Analog Ground - Analog Power Supply O 600 Driver Output O Line Output for Speaker I External Input I Melody Input L ch I Melody Input R ch I RING Input I RXI Input - Capacitor Connection Terminal for PLL Loop Filter O Master Clock Output I Master Clock Input
PAD
PAD
PAD
A
100k (TYP) PAD
B
200k (TYP) PAD
C
PAD
D
E
F
PAD
PAD
G
H
Fig.36 Equivalent Circuit Diagrams (BU7858KN)
16/24
BU7893GU Matrix No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 E3 C6 E6 D6 A3 A2 B4 B1 A5 B5 D5 B6 A4 C5 E2 E4 F3 B3 F2 B2 E1 C1 D1 C2 E5 F4 F5 D2 F6 F1 A1 A6 AVDD AVSS ANAINL ANAINR HPOL HPOR CCL CCR SPOL SPOR COMOUT COMIN CPOP CSTEP PLLC DVDD_CORE DVDD_IO DVSS CLKI RSTB CSB SCLK SIO SO SDI BCLK LRCLK MCLK TEST1 TEST2 TEST3 TEST4 I I Analog Power Supply Analog Ground DAC L-ch Input DAC R-ch Input Terminal Pin Name I/O Pin Function Conditions at Reset Pull-down Pull-down Pull-down Pull-down Pull-down Pull-down Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Pull-down Pull-down AVDD AVDD AVDD AVDD AVDD AVDD AVDD AVDD AVDD AVDD AVDD AVDD AVDD AVDD AVDD DVDD_CORE DVDD_IO DVDD_IO, DVDD_CORE DVDD_IO DVDD_IO DVDD_IO DVDD_IO DVDD_IO DVDD_IO DVDD_IO DVDD_IO DVDD_IO DVDD_IO DVDD_IO DVDD_IO DVDD_IO AVDD Power Equivalent Circuit Diagram G G H H I I H H J K L L L D A B A F E C E E E C C E
No.
O Headphone Amplifier Output L-ch O Headphone Amplifier Output R-ch I I Low-band Correction Capacitor for Headphone Amplifier Amplifier L-ch R-ch Low-band Correction Capacitor for Headphone
O L-ch Line Output for Speaker O R-ch Line Output for Speaker O Analog Reference Voltage Output I I/O I/O Analog Reference Voltage Input Capacitor Connection Terminal for Pop Noise Reduction Capacitor Connection Terminal for Noise Reduction during Volume Change Digital Core Power Supply Digital IO Power Supply Digital Ground PLL Reference Clock Input (19.2/19.68/19.8 MHz) Reset Input L: Reset CPU Interface Select Pin (L CPU I/F DVDD_IO I2C I/F) CPU Interface Clock CPU Interface Data Input/Output (at Reset Input) CPU Interface Data Output (connected to DVSS when not in use) Audio DAC Digital Data Input
I/O Capacitor Connection Terminal for PLL Loop Filter I I I I I/O I/O I
I/O Audio DAC Bit Clock (Input State at Reset) I/O Audio DAC LR Clock (Input State at Reset) I/O Audio DAC Master Clock (Input State at reset ) I I Test Pin (connected to DVSS during normal operation) Test Pin (connected to DVSS during normal operation) Test Pin (released during normal operation)
I/O Test Pin (released during normal operation) I
17/24
Schmitt Trigger
IN
PAD
IN
PAD
IN
PAD
A
B
C
Schmitt Trigger
IN
PAD
INOUT
PAD
INOUT
PAD
D
E
F
IN
PAD
+
OUT
PAD
IN
PAD
G
H
I
IN/OUT + OUT PAD PAD
IN/OUT PAD
J
K
L
Fig.37 Equivalent Circuit Diagrams (BU7893GU)
18/24
RECOMMENDED SEQUENCE BU7858KN
Mode Setting Flow
Power Supply ON
Power Supply OFF
Reference Voltage ON (VCOM=1)
Stand-by mode
Input Path Setting Mixing Path Setting
RESET NRST=0 or PLLPDN=0, VCOM=0
Analog Power ON (PDN=1)
*1
HPAMP RESET (HPRST=0)
*2
PLL Setting (PLLPDN=1) (Using PLL)
Analog Power OFF (PDN=0)
DAC Setting (Using DAC)
*1
PLL OFF (PLLPDN=0) (Using PLL)
DAC MUTE OFF (Using DAC)
DAC MUTE ON (Using DAC)
HPAMP RESET Lifting (Using HPAMP)
HPAMP MUTE ON (Using HPAMP)
Play
*1 : When the analog path setting is not changed (Repeated play) *2 : When the power supply OFF, after playing
Fig.38 BU7858KN Recommended Sequence Flow Chart
19/24
BU7893GU SAMPLE# AUDIO PATH+ AUDIO DAC BLOCK SETTING SEQUENCE After powering up and canceling reset, set paths according to the sequence shown as below: (1) Start up reference voltage Start up the reference voltage in the REF_PWR register (00h). To start up the VREF block fast, set the REF_ON bit (bit-0) and BST_ON bit (bit-1) to "1" simultaneously. up the reference voltage startup, set just the BST_ON bit (bit-1) to "0".
After starting
(2) Start up Audio DAC When using Audio DAC (2-1) Enable PLL block clock input and start up PLL Start up the power supply of the PLL and enable clock input to the PLL in the PLL_PWR register (16h). Set REF1_ON (bit-1) and PLL_ON (bit-0) to "1" simultaneously. (2-2) Caution concerning interim between starting up PLL block and starting up Audio DAC block After starting up the power supply of the PLL in the PLL_PWR register (16h), wait 10 msec before starting up the Audio DAC. (2-3) Start up Audio DAC block Start up the power supply of the Audio DAC in the DAC SET4 register (13h). Set DAC_ON (bit-5) and DAC_RSTB (Bit-4) to "1". (2-4) Set 3D surround and Equalyzer parameter Please tell us about the parameter setting when you use this function. (3) Start up analog input amplifier to use Start up the power supply of the input amplifier and input volume in the IAMP_PWR register (01h). (4) Set input volume Set the input volume in the IVR_1 register (09h). (5) Set mixing path Make mixing path settings in the MIX1 register (02h), MIX2 register (03h), MIX3 register (04h), and MIX4 register (05h). (6) Set startup noise reduction sequence Set the sequence time in the POP_TM register (07h). (7) Set click noise reduction sequence Set the sequence time in the OVR_TM register (0Ah). (8) Set output path Enable the relevant output path in the PATH_CNT register (06h). (9) Set output volume Set output volume values =0x18(-48dB) in the OVR_1 register (0Bh). (10) Ramp up output driver amplifier Ramp up the output driver amplifier in the DRV_PWR register (08h). (11) Caution concerning interim between ramping up output driver amplifier and canceling mute After setting the DRV_PWR register (08h), wait the sequence time set in the POP_TM register (07h) before canceling mute. (12) Cancel mute Cancel mute state of the output driver amplifier in the DRV_MT register (0Ch). (13) Caution concerning interim between canceling mute and setting output volume After setting the DRV_MT register (0Ch), wait the sequence time that is set in the OVR_TM register (0Ah) before subsequently setting output volume. (14) Set output volume Set output volume values in the OVR_1 register (0Bh).
20/24
PATH MODIFICATION SEQUENCE (1) Set output mute Put the output driver amplifier in a mute state by setting the DRV_MT register (0Ch). (2) Caution concerning interim between setting mute and ramping down output driver amplifier After setting the DRV_MT register (0Ch), wait the sequence time that is set in the OVR_TM register (0Ah) before subsequently ramping down the output driver amplifier. (3) Ramp down output driver amplifier Ramp down the output driver amplifier by setting the DRV_PWR register (08h). (4) Set AUDIO DAC (Refer to P.20) (5) Modify input path, mixing path, output path (Refer to P.20) (6) Ramp up output driver amplifier Ramp up output driver amplifier in the DRV_PWR register (08h) After ramping down output driver at (3), wait the sequence time that is set in the POP_TM register (07h) before subsequently ramping up. (7) Caution concerning interim between ramping up output driver amplifier and canceling mute After setting the DRV_PWR register (08h) at (6), wait the sequence time that is set in the POP_TM register (07h) before subsequently canceling mute. (8) Cancel mute Cancel output mute in the DRV_MT register (0Ch). POWER-DOWN SEQUENCE (1) Set output volume Set output volume values =0x18(-48dB) in the OVR_1 register (0Bh). (2) Caution concerning interim between setting output volume and setting mute After setting the OVR_1 register (0Bh), wait the sequence time that is set in the DRV_MT register (0Ch) before subsequently setting mute. (3) Put the output driver amplifier in a mute state by using the DRV_MT register (0Ch). (4) Caution concerning interim between setting mute and ramping down output driver amplifier After setting the DRV_MT register (0Ch), wait the sequence time that is set in the OVR_TM register (0Ah) before subsequently ramping down the output driver amplifier. (5) Ramp down output driver amplifier Ramp down the output driver amplifier in the DRV_PWR register (08h). (6) Power down AUDIO DAC When using AUDIO DAC (6-1) Power down AUDIO DAC block Power down the AUDIO DAC according to the DAC SET4 register (13h). Set DAC_ON (bit-5) and DAC_RSTB (Bit-4) to "0". (6-2) Mask clock input and power down PLL block Power down the PLL and mask clock input to the PLL according to the PLL_PWR register (16h). Set REF_ON (bit-1) and PLL_ON (bit-0) to "0" simultaneously. (7) Input reset Put a reset state by using RSTB pin input. (8) Power down
21/24
CAUTION ON USE 1) Absolute Maximum Ratings An excess in the absolute maximum ratings, such as supply voltage, temperature range of operating conditions, etc., can break down the devices, thus making impossible to identify breaking mode such as a short circuit or an open circuit. If any special mode exceeding the absolute maximum ratings is assumed, consideration should be given to take physical safety measures including the use of fuses, etc. Operating conditions These conditions represent a range within which characteristics can be provided approximately as expected. The electrical characteristics are guaranteed under the conditions of each parameter.
2)
3) Reverse connection of power supply connector The reverse connection of power supply connector can break down ICs. Take protective measures against the breakdown due to the reverse connection, such as mounting an external diode between the power supply and the IC's power supply terminal. 4) Power supply line Design PCB pattern to provide low impedance for the wiring between the power supply and the GND lines. In this regard, for the digital block power supply and the analog block power supply, even though these power supplies has the same level of potential, separate the power supply pattern for the digital block from that for the analog block, thus suppressing the diffraction of digital noises to the analog block power supply resulting from impedance common to the wiring patterns. For the GND line, give consideration to design the patterns in a similar manner. Furthermore, for all power supply terminals to ICs, mount a capacitor between the power supply and the GND terminal. At the same time, in order to use an electrolytic capacitor, thoroughly check to be sure the characteristics of the capacitor to be used present no problem including the occurrence of capacity dropout at a low temperature, thus determining the constant. GND voltage Make setting of the potential of the GND terminal so that it will be maintained at the minimum in any operating state. Furthermore, check to be sure no terminals are at a potential lower than the GND voltage including an actual electric transient. Short circuit between terminals and erroneous mounting In order mount ICs on a set PCB, pay thorough attention to the direction and offset of the ICs, Erroneous mounting can break down the ICs. Furthermore, if a shout circuit occurs due to foreign matters entering between terminals or between the terminal and the power supply or the GND terminal, the ICs can break down. Operation in a strong electromagnetic field Be noted that using ICs in the strong electromagnetic field can malfunction them. Inspection with set PCB On the inspection with the set PCB, if a capacitor is connected to a low-impedance IC terminal, the IC can suffer stress. Therefore, be sure to discharge from the set PCB by each process. Furthermore, in order to mount or dismount the set PCB to/from the jig for the inspection process, be sure to turn OFF the power supply and then mount the set PCB to the jig. After the completion of the inspection, be sure to turn OFF the power supply and then dismount it from the jig. In addition, for protection against static electricity, establish a ground for the assembly process and pay thorough attention to the transportation and the storage of the set PCB. Input terminals In terms of the construction of IC, parasitic elements are inevitably formed in relation to potential. The operation of the parasitic element can cause interference with circuit operation, thus resulting in a malfunction and then breakdown of the input terminal. Therefore, pay thorough attention not to handle the input terminals, such as to apply to the input terminals a voltage lower than the GND respectively, so that any parasitic element will operate. Furthermore, do not apply a voltage to the input terminals when no power supply voltage is applied to the IC. In addition, even if the power supply voltage is applied, apply to the input terminals, a voltage lower than the power supply voltage or within the guaranteed value of electrical characteristics.
5)
6)
7) 8)
9)
10) Ground wiring pattern If small-signal GND and large-current GND are provided, It will be recommended to separate the large-current GND pattern from the small-signal GND pattern and establish a single ground at the reference point of the set PCB so that resistance to the wiring pattern and voltage fluctuations due to a large current will cause no fluctuations in voltages of the small-signal GND. Pay attention not to cause fluctuations in the GND wiring pattern of external parts as well. 11) External capacitor In order to use a ceramic capacitor as the external capacitor, determine the constant with consideration given to a degradation in the normal capacitance due to DC bias and changes in the capacitance due to temperature, etc. 12) No Connecting input terminals In terms of extremely high impedance of CMOS gate, to open the input terminals causes unstable state. And unstable state brings the inside gate voltage of p-channel or n-channel transistor into active. As a result, battery current may increase. And unstable state can also causes unexpected operation of IC. So unless otherwise specified, input terminals not being used should be connected to the power supply or GND line.
22/24
PARTS ORDER NUMBER
B
U
7
8
5
8
K
N
E
2
ROHM Parts Code
Model No.
Package Code KN=VQFN
Taping Code E2=Reel type, Embossed carrier tape
B
U
7
8
9
3
G
U
E
2
ROHM Parts Code
Model No.
Package Code GU=VCSP
Taping Code E2=Reel type, Embossed carrier tape
VQFN28

5.20.1 5.00.1
21 22 15 14

Tape Embossed carrier tape(with dry pack) 2500pcs E2
(The direction is the 1pin of product is at the upper left when you hold reel on the left hand and you pull out the tape on the right hand)
(1.1)
Quantity
5.00.1 5.20.1
Direction of feed
.3 (0 3-
1
0.220.05
0.22 0.05
7
+0.03 0.02 -0.02 0.95MAX
0.5
0.05
(0
28
8
.2
2)
. (0 5)
5)
1234
1234
1234
1234
1234
1234
+0.1 (0.6 -0.3)
0.05
(Unit:mm)
Reel
1pin
Direction of feed
When you order , please order in times the amount of package quantity.
VCSP85H3/BU7893GU

Tape Quantity Direction of feed Embossed carrier tape 2500pcs E2
(The direction is the 1pin of product is at the upper left when you hold reel on the left hand and you pull out the tape on the right hand)
1234
1234
1234
1234
1234
1234
Reel
1Pin
Direction of feed
(Unit:mm)
When you order , please order in times the amount of package quantity.
23/24
Catalog No.07T253A '07.10 ROHM (c)
Appendix
Notes
No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM CO.,LTD. The content specified herein is subject to change for improvement without notice. The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM upon request. Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production. Great care was taken in ensuring the accuracy of the information specified in this document. However, should you incur any damage arising from any inaccuracy or misprint of such information, ROHM shall bear no responsibility for such damage. The technical information specified herein is intended only to show the typical functions of and examples of application circuits for the Products. ROHM does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by ROHM and other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. The Products specified in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices). The Products are not designed to be radiation tolerant. While ROHM always makes efforts to enhance the quality and reliability of its Products, a Product may fail or malfunction for a variety of reasons. Please be sure to implement in your equipment using the Products safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any Product, such as derating, redundancy, fire control and fail-safe designs. ROHM shall bear no responsibility whatsoever for your use of any Product outside of the prescribed scope or not in accordance with the instruction manual. The Products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury (such as a medical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuel-controller or other safety device). ROHM shall bear no responsibility in any way for use of any of the Products for the above special purposes. If a Product is intended to be used for any such special purpose, please contact a ROHM sales representative before purchasing. If you intend to export or ship overseas any Product or technology specified herein that may be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to obtain a license or permit under the Law.
Thank you for your accessing to ROHM product informations. More detail product informations and catalogs are available, please contact your nearest sales office.
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